1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory and a manufacturing method thereof.
2. Description of the Related Art
Among the various types of non-volatile memory products, electrically erasable programmable read only memory (EEPROM) is a memory device that has been widely used inside personal computer systems and electron equipment. In the EEPROM, data can be stored, read out or erased numerous times and stored data is retained even after power is cut off.
Typically, the floating gates and the control gates of EEPROM cells are fabricated using doped polysilicon. To prevent errors in reading data from an EEPROM due to over-erasing, an additional select gate is disposed on the sidewalls of the control gate and the floating gate above the substrate to form a split-gate structure.
At present, the manufacturing industry has successfully produced an AG-AND type memory structure composed of the split gate memory cells. FIG. 1 is a schematic cross-sectional view of a conventional AG-AND memory structure.
As shown in FIG. 1, the a single memory cell of the AG-AND memory includes a substrate 100, an assist gate structure 102, a tunneling dielectric layer 104, a floating gate 106, an inter-gate dielectric layer 108, a word line 110 (a control gate), a source/drain region 112 and another source/drain region 114. The assist gate structure 102 includes a gate dielectric layer 116, an assist gate 118, a cap layer 120 and a pair of spacers 122. In an AG-AND array, every pair of adjacent memory cells in the same row uses a common source/drain region.
As the level of integration of integrated circuits continues to increase and the dimensions of each device continues to shrink, the dimensions of the AG-AND memory cells can be reduced through a reduction in the width of the assist gate or the width of the floating gate. However, the reduction of assist gate width leads to a shorter length of the channel underneath the gate oxide layer 116. As a result, assist gate leakage between neighboring memory cells will easily occur when the memory cells are programmed and hence lead to an increase in programming disturbance. Thus, the electrical performance of the memory cells can be seriously affected. Consequently, a minimum width must be maintained for the assist gate 102.
On the other hand, the voltage needed to operate the memory cells is inversely proportional to the gate-coupling ratio (GCR) between the floating gate and the control gate. However, any reduction in the width of the floating gate will lead to a diminution of the overlapping area between the word line 110 (the control gate) and the floating gate and a reduction of the gate-coupling ratio so that voltage for operating the memory cells need to be increased. With the present trend of miniaturizing electronic devices, finding a method capable of maintaining a definite gate-coupling ratio in the memory cells and reliability in the memory devices within a limited space is an important research activity.